This article continues to be accepted to get inclusion in a future concern of this journal. Content can be final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SIZE INTEGRATION (VLSI) SYSTEMS
32 BitГ—32 Bit Multiprecision Razor-Based Powerful
Voltage Running Multiplier With Operands Scheduler
Xiaoxiao Zhang, Student Affiliate, IEEE, Farid Boussaid, Older Member, IEEE, and Amine Bermak, Many other, IEEE
AbstractвЂ” In this daily news, we present a multiprecision (MP)
reconп¬Ѓgurable multiplier that incorporates changing precision, parallel processing (PP), razor-based active voltage climbing (DVS), and dedicated MP operands organizing to provide ideal performance for a variety of working conditions. All the building blocks from the proposed reconп¬Ѓgurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision epreuve. Given the user's requirements (e. g., throughput), a dynamic voltage/frequency scaling administration unit conп¬Ѓgures the multiplier to operate on the proper precision and rate of recurrence. Adapting
for the run-time work load of the targeted application, razor blade
п¬‚ip-п¬‚ops as well as a dithering voltage product then conп¬Ѓgure the multiplier to achieve the most affordable power ingestion. The
single-switch dithering ac electricity unit and razor п¬‚ip-п¬‚ops help to reduce the voltage security margins and overhead typically
associated to DVS towards the lowest level. The top silicon location and power overhead commonly associated to reconп¬Ѓgurability features are taken off. Finally, the proposed book MP multiplier can even more beneп¬Ѓt by an operands scheduler that rearranges the input data, hence to look for the optimum ac electricity and
rate of recurrence operating circumstances for bare minimum power intake. This low-power MP multiplier is fabricated in AMIS 0. 35-Вµm
technology. Experimental results show that the recommended MP
design and style features a twenty-eight. 2% and 15. 8% reduction in signal area
and power intake compared with regular п¬Ѓxed-width multiplier. When merging this MP design with error-tolerant razor-based DVS, PP, plus the proposed story operands scheduler, 77. 7%вЂ“86. 3% total power lowering is obtained with a total silicon area overhead just 11. 1%. This newspaper successfully displays that a MEGA-PIXEL architecture enables more aggressive frequency/supply ac electricity scaling to get improved electrical power efп¬Ѓciency. Index TermsвЂ” Pc arithmetic, active voltage running, low electricity design, multi-precision multiplier.
I. I NTRODUCTION
ONSUMERS demand for significantly portable yet highperformance multimedia system and communication products imposes stringent constraints on the power consumption of
individual inner components вЂ“. Of such, multipliers perform one of the most often encountered arithmetic
Manuscript received June almost 8, 2012; revised February 10, 2013; recognized February twenty, 2013. This kind of work was supported in part by a give from the HASTKRAFTER Research Grant Council, below Grant 610509 and the Australian Research Council's Discovery Jobs Funding Scheme under Scholarhip DP130104374. X. Zhang and A. Bermak are together with the Department of Electronic and Computer Engineering, Hong Kong College or university of Research and Technology, Hong Kong (e-mail: [email protected] hk; [email protected] hk).
F. Boussaid is with the college of Electrical, Electronic, and Computer Executive, The University of Traditional western Australia, Perth 6017, Sydney (e-mail: farid. [email protected] edu. au).
Color versions of just one or more with the п¬Ѓgures with this paper can be obtained online by http://ieeexplore.ieee.org.
Digital Object Identiп¬Ѓer 10. 1109/TVLSI. 2013. 2252032
operations in digital sign processors (DSPs) . For embedded applications, it is now essential to design and style more power-aware multipliers вЂ“. Provided their quite complex structure and interconnections, multipliers can exhibit many unbalanced paths, resulting in substantial glitch
generation and propagation , . This spurious...